SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
Hewlett-Packard Company
AlphaServer ES47 7/1000
SPECint2000 = 761    
SPECint_base2000 = 689    
SPEC license # 2 Tested by: HP Test date: Dec-2002 Hardware Avail: Jan-2003 Software Avail: Jan-2003
Benchmark Reference
Runtime Ratio Graph Scale
164.gzip 1400 276    507     272    515     164.gzip base result bar (507)
164.gzip peak result bar (515)
175.vpr 1400 196    713     191    734     175.vpr base result bar (713)
175.vpr peak result bar (734)
176.gcc 1100 147    746     132    834     176.gcc base result bar (746)
176.gcc peak result bar (834)
181.mcf 1800 291    619     182    988     181.mcf base result bar (619)
181.mcf peak result bar (988)
186.crafty 1000 117    856     117    856     186.crafty base result bar (856)
186.crafty peak result bar (856)
197.parser 1800 404    446     318    566     197.parser base result bar (446)
197.parser peak result bar (566)
252.eon 1300 156    831     158    822     252.eon base result bar (831)
252.eon peak result bar (822)
253.perlbmk 1800 273    660     256    703     253.perlbmk base result bar (660)
253.perlbmk peak result bar (703)
254.gap 1100 199    553     177    621     254.gap base result bar (553)
254.gap peak result bar (621)
255.vortex 1900 201    947     183    1041      255.vortex base result bar (947)
255.vortex peak result bar (1041)
256.bzip2 1500 210    715     199    755     256.bzip2 base result bar (715)
256.bzip2 peak result bar (755)
300.twolf 3000 341    881     336    892     300.twolf base result bar (881)
300.twolf peak result bar (892)
SPECint_base2000 689      
  SPECint2000 761      

Hardware Vendor: Hewlett-Packard Company
Model Name: AlphaServer ES47 7/1000
CPU: Alpha 21364
CPU MHz: 1000
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip
CPU(s) orderable: 2 to 4
Parallel: No
Primary Cache: 64KB(I)+64KB(D) on chip
Secondary Cache: 1.75MB on chip per CPU
L3 Cache: None
Other Cache: None
Memory: 4GB
Disk Subsystem:
Other Hardware: None
Operating System: Tru64 UNIX V5.1B (Rev. 2650)
Compiler: Compaq C V6.5-011-48C5K
Program Analysis Tools V2.0
Spike V5.2 (506A)
Compaq C++ V6.5-028
File System: ufs
System State: Multi-user
Notes / Tuning Information
 Baseline C  : cc  -arch ev7 -fast +CFB ONESTEP 
          C++: cxx -arch ev7 -O2        ONESTEP 
   The following use: -g3 -arch ev7 ONESTEP
       175.vpr 181.mcf 197.parser 253.perlbmk

   The following use: -g3 -arch ev6 ONESTEP
       164.gzip 176.gcc 254.gap 255.vortex 256.bzip2 300.twolf

   Individual benchmark tuning:
      164.gzip: -fast -O4 -non_shared +CFB 
       175.vpr: -fast -O4 -assume restricted_pointers +CFB 
       176.gcc: -fast -O4 -xtaso_short -all -ldensemalloc -none
                +CFB +IFB 
       181.mcf: -fast -xtaso_short +CFB +IFB +PFB
    186.crafty: same as base
    197.parser: -fast -O4 -xtaso_short -non_shared +CFB
       252.eon: -arch ev7 -O2 -all -ldensemalloc -none 
   253.perlbmk: -fast -non_shared +CFB +IFB 
       254.gap: -fast -O4 -non_shared +CFB +IFB +PFB 
    255.vortex: -fast -non_shared +CFB +IFB
     256.bzip2: -fast -O4 -non_shared +CFB 
     300.twolf: -fast -O4 
                -ldensemalloc -non_shared +CFB +IFB

 Most benchmarks are built using one or more types of 
 profile-driven feedback.  The types used are designated
 by abbreviations in the notes:

 +CFB: Code generation is optimized by the compiler, using 
       feedback from a training run.  These commands are
       done before the first compile (in phase "fdo_pre0"):

            mkdir /tmp/pp
            rm -f /tmp/pp/${baseexe}*

       and these flags are added to the first and second compiles:

            PASS1_CFLAGS = -prof_gen_noopt -prof_dir /tmp/pp
            PASS2_CFLAGS = -prof_use       -prof_dir /tmp/pp
      (Peak builds use /tmp/pp above; base builds use /tmp/pb.)

 +IFB: Icache usage is improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These commands
       are used (in phase "fdo_postN"):  

            mv ${baseexe} oldexe
            spike oldexe -feedback oldexe -o ${baseexe}

 +PFB: Prefetches are improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These
       commands are used (in phase "fdo_post_makeN"):

            rm -f *Counts*
            mv ${baseexe} oldexe
            pixie -stats dstride oldexe 1>pixie.out 2>pixie.err
            mv oldexe.pixie ${baseexe}

       A training run is carried out (in phase "fdo_runN"), and 
       then this command (in phase "fdo_postN"):

            spike oldexe -fb oldexe -stride_prefetch -o ${baseexe}

 When Spike is used for both Icache and Prefetch improvements, 
 only one spike command is actually issued, with the Icache 
 options followed by the Prefetch options.
 Portability: gcc: -Dalloca=__builtin_alloca; crafty: -DALPHA
 perlbmk: -DSPEC_CPU2000_DUNIX; vortex: -DSPEC_CPU2000_LP64
 Information on UNIX V5.1B Patches can be found at
         vm_bigpg_enabled = 1
         vm_swap_eager = 0

         max_per_proc_address_space = 0x40000000000
         max_per_proc_data_size = 0x40000000000
         max_per_proc_stack_size = 0x40000000000
         max_proc_per_user = 2048
         max_threads_per_user = 0
         maxusers = 16384
         per_proc_address_space = 0x40000000000
         per_proc_data_size = 0x40000000000
         per_proc_stack_size = 0x40000000000

 In the ES47, there are two cpus per shelf.  Each cpu has
 its own 4GB of memory.  Neither of the cpus can be 
 physically removed.  For 1 cpu results measured on a 2 cpu
 system, one cpu was turned off at boot time using the
 /etc/sysconfigtab setting "cpu_enabled_mask=0".  The cpu's
 4GB of memory was also physically removed.

For questions about this result, please contact the tester.
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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 28-Jan-2003

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