SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
Hewlett-Packard Company
hp AlphaServer ES45 68/1250
SPECint2000 = 928    
SPECint_base2000 = 845    
SPEC license # 2 Tested by: HP NH Test date: Jul-2002 Hardware Avail: Aug-2002 Software Avail: Dec-2002
Benchmark Reference
Runtime Ratio Graph Scale
164.gzip 1400 243    575     240    583     164.gzip base result bar (575)
164.gzip peak result bar (583)
175.vpr 1400 163    860     159    880     175.vpr base result bar (860)
175.vpr peak result bar (880)
176.gcc 1100 122    905     112    986     176.gcc base result bar (905)
176.gcc peak result bar (986)
181.mcf 1800 160    1125      123    1465      181.mcf base result bar (1125)
181.mcf peak result bar (1465)
186.crafty 1000 98.4  1016      98.4  1016      186.crafty base result bar (1016)
186.crafty peak result bar (1016)
197.parser 1800 316    569     256    704     197.parser base result bar (569)
197.parser peak result bar (704)
252.eon 1300 137    952     132    988     252.eon base result bar (952)
252.eon peak result bar (988)
253.perlbmk 1800 228    790     208    864     253.perlbmk base result bar (790)
253.perlbmk peak result bar (864)
254.gap 1100 199    552     164    670     254.gap base result bar (552)
254.gap peak result bar (670)
255.vortex 1900 164    1158      145    1309      255.vortex base result bar (1158)
255.vortex peak result bar (1309)
256.bzip2 1500 162    925     150    998     256.bzip2 base result bar (925)
256.bzip2 peak result bar (998)
300.twolf 3000 292    1026      292    1026      300.twolf base result bar (1026)
300.twolf peak result bar (1026)
SPECint_base2000 845      
  SPECint2000 928      

Hardware Vendor: Hewlett-Packard Company
Model Name: hp AlphaServer ES45 68/1250
CPU: Alpha 21264C
CPU MHz: 1250
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip
CPU(s) orderable: 1 to 4
Parallel: No
Primary Cache: 64KB(I)+64KB(D) on chip
Secondary Cache: 16MB off chip per CPU
L3 Cache: None
Other Cache: None
Memory: 16GB
Disk Subsystem: 9 GB SCSI
Other Hardware: None
Operating System: Tru64 UNIX V5.1B
Compiler: Compaq C V6.5-011-48C5K
Spike V5.2 (506 48C5K)
Compaq C++ V6.3-010
File System: ufs
System State: Multi-user
Notes / Tuning Information
 Baseline C  : cc  -arch ev6 -fast +CFB ONESTEP 
          C++: cxx -arch ev6 -O2        ONESTEP 
   All but 252.eon: cc -g3 -arch ev6 ONESTEP
      164.gzip: -fast -O4 -non_shared +CFB 
       175.vpr: -fast -O4 -assume restricted_pointers +CFB 
       176.gcc: -fast -O4 -xtaso_short -all -ldensemalloc -none
                +CFB +IFB 
       181.mcf: -fast -xtaso_short +CFB +IFB +PFB
    186.crafty: same as base
    197.parser: -fast -O4 -xtaso_short -non_shared +CFB
       252.eon: cxx -arch ev6 -O2 -all -ldensemalloc -none 
   253.perlbmk: -fast -non_shared +CFB +IFB 
       254.gap: -fast -O4 -non_shared +CFB +IFB +PFB 
    255.vortex: -fast -non_shared +CFB +IFB
     256.bzip2: -fast -O4 -non_shared +CFB 
     300.twolf: -fast -O4 
                -ldensemalloc -non_shared +CFB +IFB

 Most benchmarks are built using one or more types of 
 profile-driven feedback.  The types used are designated
 by abbreviations in the notes:

 +CFB: Code generation is optimized by the compiler, using 
       feedback from a training run.  These commands are
       done before the first compile (in phase "fdo_pre0"):

            mkdir /tmp/pp
            rm -f /tmp/pp/${baseexe}*

       and these flags are added to the first and second compiles:

            PASS1_CFLAGS = -prof_gen_noopt -prof_dir /tmp/pp
            PASS2_CFLAGS = -prof_use       -prof_dir /tmp/pp
      (Peak builds use /tmp/pp above; base builds use /tmp/pb.)

 +IFB: Icache usage is improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These commands
       are used (in phase "fdo_postN"):  

            mv ${baseexe} oldexe
            spike oldexe -feedback oldexe -o ${baseexe}

 +PFB: Prefetches are improved by the post-link-time optimizer 
       Spike, using feedback from a training run.  These
       commands are used (in phase "fdo_post_makeN"):

            rm -f *Counts*
            mv ${baseexe} oldexe
            pixie -stats dstride oldexe 1>pixie.out 2>pixie.err
            mv oldexe.pixie ${baseexe}

       A training run is carried out (in phase "fdo_runN"), and 
       then this command (in phase "fdo_postN"):

            spike oldexe -fb oldexe -stride_prefetch -o ${baseexe}

 When Spike is used for both Icache and Prefetch improvements, 
 only one spike command is actually issued, with the Icache 
 options followed by the Prefetch options.
         vm_bigpg_enabled = 1
         vm_swap_eager = 0
         max_per_proc_address_space = 0x40000000000
         max_per_proc_data_size = 0x40000000000
         max_per_proc_stack_size = 0x40000000000
         max_proc_per_user = 2048
         max_threads_per_user = 0
         maxusers = 16384
         per_proc_address_space = 0x40000000000
         per_proc_data_size = 0x40000000000
         per_proc_stack_size = 0x40000000000
 Portability: gcc: -Dalloca=__builtin_alloca; crafty: -DALPHA
 perlbmk: -DSPEC_CPU2000_DUNIX; vortex: -DSPEC_CPU2000_LP64

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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 12-Nov-2002

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