SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 590 (1650 MHz, 1 CPU)
SPECint2000 = 1259     
SPECint_base2000 = 1200     
SPEC license # 11 Tested by: IBM Test date: Sep-2004 Hardware Avail: Nov-2004 Software Avail: Nov-2004
Benchmark Reference
Time		 Base
Runtime		 Base
Ratio		 Runtime Ratio Graph Scale
164.gzip 1400 187    749     183    766     164.gzip base result bar (749)
164.gzip peak result bar (766)
175.vpr 1400 132    1064      132    1062      175.vpr base result bar (1064)
175.vpr peak result bar (1062)
176.gcc 1100 82.1  1339      81.5  1350      176.gcc base result bar (1339)
176.gcc peak result bar (1350)
181.mcf 1800 86.9  2072      80.1  2246      181.mcf base result bar (2072)
181.mcf peak result bar (2246)
186.crafty 1000 97.6  1025      79.0  1265      186.crafty base result bar (1025)
186.crafty peak result bar (1265)
197.parser 1800 168    1068      166    1083      197.parser base result bar (1068)
197.parser peak result bar (1083)
252.eon 1300 93.6  1389      90.5  1437      252.eon base result bar (1389)
252.eon peak result bar (1437)
253.perlbmk 1800 214    843     196    920     253.perlbmk base result bar (843)
253.perlbmk peak result bar (920)
254.gap 1100 99.1  1110      99.1  1110      254.gap base result bar (1110)
254.gap peak result bar (1110)
255.vortex 1900 103    1846      96.6  1967      255.vortex base result bar (1846)
255.vortex peak result bar (1967)
256.bzip2 1500 131    1142      128    1172      256.bzip2 base result bar (1142)
256.bzip2 peak result bar (1172)
300.twolf 3000 223    1348      216    1389      300.twolf base result bar (1348)
300.twolf peak result bar (1389)
SPECint_base2000 1200       
  SPECint2000 1259       

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 590 (1650 MHz, 1 CPU)
CPU: POWER5
CPU MHz: 1650
FPU: Integrated
CPU(s) enabled: 1 core, 1 chip, 1 core/chip (SMT off)
CPU(s) orderable: 8,16,24,32
Parallel: No
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off-chip)/chip, 4 chips/MCM, 4 MCMs/SUT
Other Cache: None
Memory: 128 GB DDR1
Disk Subsystem: 2x36GB SCSI, 15K RPM
Other Hardware: None
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition V7.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information 
Tested by IBM
  Portability Flags:
    176.gcc:          EXTRA_CFLAGS=-ma -DHOST_WORDS_BIG_ENDIAN
    186.crafty:       EXTRA_CFLAGS=-DAIX
    252.eon:          EXTRA_LDFLAGS=-I. -DNDEBUG
    253.perlbmk:      EXTRA_CFLAGS=-DSPEC_CPU2000_AIX
    254.gap:          EXTRA_CFLAGS=-DSYS_IS_BSD -DSYS_STRING_H -DSYS_HAS_TIME_PROTO -DSYS_HAS_MALLOC_PROTO
                                   -DSYS_HAS_CALLOC_PROTO
    300.twolf:        EXTRA_CFLAGS=-DHAVE_SIGNED_CHAR
 
  Base Optimization Flags:
    C:     -qpdf1/pdf2
           -O5 -blpdata -D_ILS_MACROS
    C++:   -qpdf1/pdf2
           -O5 -lhmu -qalign=natural

  Alternate Sources for Base & Peak:
    Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
    was used with 252.eon for POSIX-compatibility.
 
  Peak Optimization Flags:
     164.gzip:       -qpdf1/pdf2
                     -O5 -blpdata -D_ILS_MACROS -qfdpr
                     fdpr -R3
     175.vpr:        -qpdf1/pdf2
                     -O5 -blpdata -qalign=natural -qhot=arraypad -Q
     176.gcc:        -qpdf1/pdf2
                     -O5
     181.mcf:        -O5 -blpdata -qfdpr -D_ILS_MACROS
                     fdpr -R3
     186.crafty:     -qpdf1/pdf2
                     -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3 -D_ILS_MACROS
                     fdpr -R3
     197.parser:     -qpdf1/pdf2
                     -O5 -blpdata -D_ILS_MACROS -qfdpr
                     fdpr -R3
     252.eon:        -qpdf1/pdf2
                     -O4 -qarch=pwr4 -qtune=pwr4 -qalign=natural -D_ILS_MACROS
     253.perlbmk:    -qpdf1/pdf2
                     -O5 -lhmu -qalign=natural
     254.gap:        -qpdf1/pdf2
                     -O5 -lhmu -qalign=natural -D_ILS_MACROS -blpdata  
     255.vortex:     -qpdf1/pdf2
                     -O5 -lhmu -qalign=natural -D_ILS_MACROS -blpdata
     256.bzip2:      -qpdf1/pdf2
                     -O5 -blpdata -D_ILS_MACROS -qfdpr
                     fdpr -R3
     300.twolf:      -O5 -blpdata -qfdpr -D_ILS_MACROS
                     fdpr -R3


  SMT: Acronym for "Simultaneous Multi-Threading". A processor technology that allows
       the simultaneous execution of multiple thread contexts within a single processor
       core. (Enabled by default)
  MCM: Acronym for "Multi-Chip Module" (four dual-core processor chips + four L3-cache chips)
       This system contains 4 MCMs.
  SUT: Acronym for "System Under Test"

  C:       IBM XL C for AIX invoked as xlc
  C++:     IBM XL C++ for AIX invoked as xlC

  APAR IY60349 was applied to AIX to enable new hardware support.
  ulimits set to unlimited.
  Large page mode and memory affinity were set as follows:
     vmo -r -o lgpg_regions=4096 -o lgpg_size=16777216 -o memory_affinity=1
     chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
     shutdown -r
     export MEMORY_AFFINITY=MCM

  Thirty-one cores were deconfigured and SMT disabled at the open-firmware prompt, using the
  command
              boot -s cpu=1 -s smt_off
  The following config-file entry was used to assign each benchmark process to a core:
     use_submit_for_speed = 1
     submit = let "MYCPU=\$SPECUSERNUM"; bindprocessor \$\$ \$MYCPU; $command
  The "bindprocessor" AIX command binds a process to a CPU core.

For questions about this result, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 02-Nov-2004

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